In general, there has been known a memory circuit including a fuse circuit that determines an output signal level based on a disconnect state of a fuse element, and a latch circuit that holds a signal level based on a fuse signal output from the fuse circuit.
FIG. 13 is a schematic view illustrating a conventional memory circuit 20. The memory circuit 20 includes a transistor P11, a resistive element R11, a fuse element H11, a transistor N11 and a latch circuit L11.
The transistor P11 has a source terminal S connected to a power supply VDD. The resistive element R11 has one end connected to a drain terminal D of the transistor P11. The fuse element H11 has one end connected to the other end of the resistive element R11. The transistor N11 has a drain terminal D connected to the other end of the fuse element H11 and a source terminal S connected to a power source VSS. Here, an electric potential of a node Nd11 at the connection point between the fuse element H11 and the resistive element R11 is output, as a fuse signal HS11, to the latch circuit L11. The latch circuit L11 holds the fuse signal HS11 in response to an input control signal S11 and outputs a signal level of the fuse signal HS11 as an output signal SS11.
FIGS. 14A to 14D illustrate signal waveforms in the memory circuit 20 as time passes, in a case where the fuse element H11 is disconnected under an output determination mode of determining a signal level of the output signal SS11 of the memory circuit 20. FIG. 14A illustrates transition of a voltage level of the power supply VDD. FIG. 14B is a signal waveform of the fuse signal HS11. FIG. 14C is a signal waveform of the control signal S11. FIG. 14D is a signal waveform of the output signal SS11. In each of FIGS. 14A to 14D, a vertical axis represents a signal level V and a horizontal axis represents time t. Times t30 to t34 are indicated as common time in FIGS. 14A to 14D. A shaded portion indicates a period in which it is uncertain whether an electric potential has a low level or a high level.
At time t30, the power supply VDD is driven. At this point of time, the power supply VDD is at 0 V and the control signal S11 and the fuse signal HS11 have a low level and a signal level of the output signal SS11 is uncertain.
At time t31, the power supply VDD rises to a rated voltage of 5 V and the transistor P11 and the transistor N11 are turned on. At this point of time, since the fuse element H11 has been disconnected, the electric potential of the node Nd11 has substantially the same voltage level as the power supply VDD and the signal level of the fuse signal HS11 becomes high, for example, about 5 V. The signal level of the high level fuse signal HS11 is given as 5 V in FIG. 14B.
At time t32, the high level control signal S11 is input to the latch circuit L11 while the signal level of the fuse signal HS11 is maintained, and the latch circuit L11 latches (holds) the high level which is the signal level of the fuse signal HS11. Thus, the signal level of the output signal SS11 becomes high, for example, about 5 V. The signal level of the high level output signal SS11 is given as 5 V in FIG. 14D.
At time t33, the control signal S11 becomes a low level, and the latch circuit L11 stops updating the signal level of the fuse signal HS11 held in the latch circuit L11. Therefore, the output signal SS11 of the latch circuit L11 is held at the high level.
At time t34, i.e., after the control signal S11 becomes the low level and the output signal SS11 of the latch circuit L11 is held at the high level, the fuse signal HS11 becomes a low level. At this point of time, since the latch circuit L11 maintains the signal level held from time t32 to time t33 during which the signal level of the fuse signal HS11 was the high level, the output signal SS11 is held at the high level.
In the memory circuit 20 described with reference to FIGS. 13 and 14A to 14D, at time t32, the control signal S11 is input to the latch circuit L11 and the signal level of the fuse signal HS11 is held in the latch circuit L11. Thereafter, at time t33, the control signal S11 supplied to the latch circuit L11 becomes a low level and the latch circuit L11 stops updating the held signal level of the fuse signal HS11 held in the latch circuit L11. Thereafter, in order to prevent the output signal SS11 from being incorrectly held due to fluctuation of the fuse signal HS11, at time t34, i.e., after sufficient time elapses from the time when the control signal S11 became the low level, the fuse signal HS11 becomes a low level and the output determination mode is terminated. Therefore, since the output determination mode needs an additional time period A from time t33 to time t34, it takes long time for a product equipped with the memory circuit 20 to reach an actually usable state after being powered on.